The IEEE Verilog 1364-2001 Standard What's New, and Why You Need It

http://www.sutherland-hdl.com/papers/2000-HDLCon-paper_Verilog-2000.pdf


3.2 Scalable models—Verilog generate


Verilog-2001 adds  generate loops, which permit generating multiple instances of modules and primitives, as well as generating multiple occurrences of variables, nets, tasks, functions, continuous assignments, initial procedures, and always procedures. Generated declarations and instantiations can be conditionally created, using if–else decisions and case statements.

3.4 Indexed vector part selects

The Verilog-2001 standard adds a new syntax, called indexed part selects. With an indexed part select, a base expression, a width expression, and an offset direction are provided, in the form of:
[base_expr +: width_expr] //positive offset
[base_expr -: width_expr] //negative offset




3.5 Multidimensional arrays
The Verilog-1995 standard allows one-dimensional arrays of variables. Verilog-2001 extends this by permitting:
• Multi-dimensional arrays
• Arrays of both variable and net data types

Verilog-Mode Emacs

http://www.veripool.org/papers/verilog-mode_veritedium_snug.pdf


Reduce spins on fixing lint or compiler warnings
ƒ Reduce sensitivity problems
- If you forget (or don’t have) a linter, these are horrible to debug!
ƒ Make it easier to name signals consistently
through the hierarchy
- Reduce cut & paste errors on multiple instantiations.
- Make it more obvious what a signal does.
ƒ Reducing the number of lines is goodness alone.
- Less code to "look" at.
- Less time typing.


This expansion is best if in the editor
• You can “see” the expansion and edit as needed
ƒ There is a Verilog package for Emacs
• Written by Michael McNamara <mac@versity.com>
• Auto highlighting of keywords
• Standardized indentation
ƒ Expanded it to read & expand /*AUTOs*/
• Magic key sequence for expand/deexpand

C-c C-a  and C-c C-d

With this key sequence,
Verilog-Mode parses the verilog code, and
expands the text after any /*AUTO*/ comments.

verilog and systemverilog real port

Subject: Literal number gotchas

There are several gotchas associated with defining literal integer numbers
in Verilog and System Verilog. There are actually two different sets of
rules involving literal integers: one that defines the generation of an
integer number, and another for assigning the number.

Many engineers have only a vague understanding of these two sets of rules,
and often confuse them with each other. Here we'll discuss gotchas on the
generation a literal integer. Sec 4.4 discusses the issues regarding the
assignment of integers.

Review of literal integer syntax. Literal integers can be specified as a
simple decimal integer (e.g. 5) or as a based integer (e.g.'h5). A based
literal integer is specified using the following syntax:

's

Where:

- is optional. If given, it specifies the total number of bits
represented by the literal value. If not given, the default size is
32 bits (the Verilog standard says "at least" 32 bits, but all
implementations the authors are aware of use exactly 32 bits).
- s is optional. If given, it specifies that the literal integer should
be treated as a 2's complemented signed value. If not given, the
default is unsigned.
- is required, and specifies whether the value is in binary,
octal, decimal, or hex.
- is required, and specifies the literal integer value.


4.1 Signed versus unsigned literal integers

Gotcha: Some literal integers default to signed; other literal
integers default to unsigned.

A simple literal integer (e.g. 5) defaults to a signed value, and cannot be
specified as unsigned. A based literal integer (e.g. 'h5) defaults to an
unsigned value, unless explicitly specified as signed (e.g. 'sh5). The s
specifier was added as part of the Verilog-2001 standard to allow the
specification of sized, signed literal values.

The difference in the default signed-ness of a value can catch engineers by
surprise. Signed-ness of a value affects several types of operations.
Unexpected operation results will occur if an engineer forgets -- or is not
aware of -- the different default signed-ness of a simple literal integer
versus a based literal integer number.

Are the following two signed counter statements the same? (Of course
not, or we wouldn't have included this example in this paper!)

byte in; // signed 8-bit variables
int out1, out2; // signed 32-bit variables

initial begin
in = -5;
out1 = in + 1; // OK: -5 + 1 = -4 (literal 1 is signed)
out2 = in + 1'b1; // GOTCHA: -5 + 1'b1 = 252 (1'b1 is unsigned)
end

How to avoid this gotcha: The difference between adding 1 and 1'b1 is that
the literal integer 1 is a signed value, whereas the literal integer 1'b1
is an unsigned value. This difference affects how the ADD operation is
performed. Signed arithmetic is discussed in more detail in Sec 5.3.


4.2 Default base of literal integers

Gotcha: Literal integers have a default base that might not be
what is intended.

A simple literal integer (e.g. 5) defaults to a decimal base. To use a
binary, octal or hex value, a based-literal number must be specified
(e.g. 'h5). The base options are represented using b, o, d, or h for
binary, octal, decimal and hex, respectively. The base specifier can be
either lower case or upper case (i.e. 'h5 and 'H5 are the same).

The following example of a 4-to-1 MUX illustrates a common gotcha when an
engineer forgets -- or is not aware -- that a simple integer number is a
decimal value:

logic [1:0] select; // 2-bit vector

always_comb begin
case (select) // intent is for a 4-to-1 MUX behavior
00: y = a;
01: y = b;
10: y = c; // GOTCHA! This branch is never selected
11: y = d; // GOTCHA! This branch is never selected
endcase
end

This gotcha fits nicely with the well known joke that only engineers laugh
at: "There are 10 types of people in the world, those that know binary, and
those that don't". The example above may look reasonable, and it is
syntactically correct. But, since the default base of a simple integer is
decimal, the values "10" and "11" are ten and eleven, respectively. The
size of the values is not specified, and so defaults to 32-bits wide. The
2-bit select signal will be zero-extended to 32-bits wide, and then compared
to zero, one, ten and eleven. The only values of select that will ever
match are a and b, which extend to 32-bit 00...00 and 00...01, respectively.
The extended value of select will never match the decimal "10" and "11".
Therefore, the c and d inputs of the multiplexer will never be selected.
Since this is not a syntax error, the problem shows up in simulation as a
functional failure which can be difficult to detect and debug. GOTCHA.

How to avoid this gotcha: to detect this use the System Verilog unique
modifier to the case statement, as in:

unique case (select) // intent is for a 4-to-1 MUX behavior

The unique modifier reports an error if two or more case select items are
true at the same time, or if no case select items are true. The example
above becomes a simulation error, rather than a functional bug in the code.

Code coverage utilities and/or System Verilog functional coverage can also
be used to detect that some branches of the case statement are not being
executed. Also, some EDA tools, such as LEDA and DC, will warn about a
mismatch in the size of select and the literal integer values to which
it is compared.


4.3 Size mismatch in literal integers

Gotcha: Too small a size truncates most-significant bits; too large
a size left-extends with...something.

Size smaller than value gotcha. Verilog rules state that if your bit size
specified is fewer bits than the value, then, no matter what, the left-most
bits of the value are truncated. This can be a gotcha when the value is
signed, because the sign bit will be truncated as well.

This can significantly affect the result of signed operations! In the
following example, a negative 15 (8-bit F1 hex) is truncated to 2-bits
wide, becoming a positive 1.

-2'sd15; // 11110001 is truncated to 01

How to avoid this gotcha: Be sure that the bit size specified is at least as
wide as the size of the value, especially when using signed values. Some
tools, such as rule checking programs like LEDA, will detect a size versus
value mismatch. Unfortunately, these tools will also report size mismatches
when using unsigned values, where a mismatch may not be a problem, and may
even be useful.

Size greater than value gotcha. Verilog rules state that when your bit size
specified is more bits than the value, then the value will be expanded to
the size by left-extending the value. The fill value used to left extend is
based on the most significant specified bit of the value, as follows:

- If the most significant bit of the value is a 0 or a 1, then the value
is left-extended zeros.
- If the most significant bit is an X, then the value is left-extended Xs.
- If the most significant bit is a Z, then the value is left-extended Zs.

This left extension can be very useful. For example, it is not necessary to
specify the value of each and every bit of a vector to reset the vector to
zero or to set the vector to high impedance.

64'h0; // fills all 64 bits with 0
64'bZ; // fills all 64 bits with Z

A surprising gotcha can occur when the bit-size is larger than the value,
and the value is signed. The expansion rules above do not sign-extend a
signed value. Even if the number is specified to be signed, and the most
significant bit is a 1, the value will still be extended by 0's. Example:

logic [11:0] a, b, c;

initial begin
a = 12'h3c; // unsigned value 00111100 expands to 000000111100
b = 12'sh3c; // signed value 00111100 expands to 000000111100
c = 12'so74; // signed value 111100 expands to 000000111100
if (a == b) ...; // evaluates as true
if (a == c) ...; // evaluates as true
end

In this example, a hex 3c is an 8-bit value, which does not set its most-
significant bit. When the value is expanded to the 12-bit size, the
expansion zero-extends, regardless of whether the value is signed or
unsigned. This is as expected.

The octal value 73 is the same bit pattern as a hex 3c, but is a 6-bit
value with its most-significant bit set. But, the expansion to the 12 bit
size still zero-extends, rather than sign-extends. If sign extension was
expected, then GOTCHA!.

How to avoid this gotcha: The subtlety in the preceding example is that the
sign bit is not the most-significant bit of the value. It is the most-
significant bit of the specified size. Thus, to specify a negative value
in the examples above, the value must explicitly set bit 12 of the literal
integer.

12'h805 // expands to 100000000101, which is 2053 decimal
12'sh805 // expands to 100000000101, which is -2043 decimal
12'shFFB // expands to 111111111011, which is -5 decimal
-12'sh5 // expands to 111111111011, which is -5 decimal

Unspecified size. If the size of a literal integer is not specified, then
the bit size of the literal number defaults to 32 bits. This default size
can be a gotcha when the is not 32 bits, as discussed earlier.


4.4 Literal number size mismatch in assignments

Gotcha: A size mismatch in literal numbers follows different rules
than a size mismatch in assignment statements.

Once a literal integer has been created and expanded via the rules in
Sec 4.3, the operator rules are then applied.

Note: This is a discussion on assignment of literal value (e.g. a = 5;)
gotchas. Sec 5 discusses assignment rules and gotchas when there are
operators on the right-hand side of the assignment.

The assignment operation rules for assigning literal values are:

- When the left-hand side expression of an assignment statement is
fewer bits than the right-hand side literal value, then the most
significant bits of the right-hand side value are truncated.
- When the left-hand side expression of an assignment statement is
more bits than the right-hand side literal value, ...
- If the right-hand side literal value is unsigned, it will be
left-extended with zeros.
- If the right-hand side literal value is signed, it will be
left-extended using sign extension.
- Exceptions: If the right-hand side is an unsized high-impedance
literal value (e.g.: 'bz) or unsized unknown (e.g.: 'bx), the value
will left-extend with Z or X, respectively, regardless of whether
signed or unsigned.

These rules might seem, at first glance, to be the same rules discussed in
Sec 4.3, when a literal integer size does not match the literal integer
value. But there is a subtle, and important difference in the rules. The
difference is that literal value expansion does not sign-extend, but an
assignment statement does sign-extend.

And now the gotcha. Sign extension of the right-hand side only occurs if
the expression on the right-hand side is signed. The signed-ness of the
left-hand side expression does not affect whether or not sign extension
will occur. Consider:

logic [3:0] a; // unsigned 4-bit variables
logic signed [3:0] b; // signed 4-bit variables
logic [7:0] u; // unsigned 8-bit variables
logic signed [7:0] s; // signed 8-bit variables

u = 4'hC; // 1100 (right-hand side) is zero-extended to 00001100
s = 4'hC; // 1100 (right-hand side) is zero-extended to 00001100
// even though s is a signed variable; GOTCHA

u = 4'shC; // 1100 (right-hand side) is sign-extended to 11111100
// even though u is an unsigned variable; GOTCHA
s = 4'shC; // 1100 (right-hand side) is sign-extended to 11111100

a = 4'hC;
u = a; // 1100 (right-hand side) is zero-extended to 00001100
s = a; // 1100 (right-hand side) is zero-extended to 00001100
// even though s is a signed variable; GOTCHA

b = 4'hC;
u = b; // 1100 (right-hand side) is sign-extended to 11111100
// even though u is an unsigned variable; GOTCHA
s = b; // 1100 (right-hand side) is sign-extended to 11111100

These simple examples illustrate two types of gotchas:

- Assigning to a signed variable does not cause sign extension. Sign
extension only occurs if the right-hand side expression is signed.

- Assigning to an unsigned variable can have sign extension. Sign
extension occurs if the right-hand side expression is signed.

In other words, it is the right-hand side of an assignment that determines
if sign extension will occur. The signed-ness of the left-hand side has no
bearing on sign extension.

These same assignment expansion rules apply when operations are performed on
the right-hand side of an assignment. However, whether zero extension or
sign extension will occur also depends on the type of operation. These
operation rules are covered in Sec 5.3.


4.5 Literal number Z and X extension backward compatibility

Gotcha: Verilog-2001 Z and X extension is not backward compatible
with Verilog-1995.

Verilog-1995 had a gotcha when assigning an unsized high-impedance value
('bz) to a bus that is greater than 32 bits. The default size of an unsized
number is 32 bits. The literal number expansion rules state the Z value
will extend through those 32 bits (see Sec 4.3). But, the assignment
extension rules state that this 32-bit value then zero-extends to the size
of the left-hand side of the assignment (see Sec 4.4). Therefore, with
Verilog-1995, only the lower 32 bits would be set to high-impedance, and the
upper bits would be set to 0. To set the entire bus to high-impedance
requires explicitly specifying the number of high impedance bits. Example:

//Verilog-1995 style:
parameter WIDTH = 64;
reg [WIDTH-1:0] data;

data = 'bz; // fills with 64'h00000000zzzzzzzz
data = 64'bz; // fills with 64'hzzzzzzzzzzzzzzzz

The fill rules in Verilog-1995 make it difficult to write models that scale
to new vector sizes. Redefinable parameters can be used to scale vector
widths, but the Verilog source code must still be modified to alter the
literal value widths used in assignment statements. (And yes, believe it or
not, there are still some companies primarily using Verilog-1995.) The
example above applies equally to assigning X's to a vector.

How to avoid this gotcha: One solution came with Verilog-2001, which changed
the rule for assignment expansion of unsized Z and X literal integers. The
unsized value of Z or X will automatically expand to fill the full width of
the vector on the left-hand side of the assignment.

//Verilog-2001style:
parameter WIDTH = 64;
reg [WIDTH-1:0] data;

data = 'bz; // fills with 64'hzzzzzzzzzzzzzzzz

The Verilog-2001 enhancement allows writing code that scales when vector
sizes are redefined. But, this solution is also a gotcha, because it is not
backward compatible w/ Verilog-1995. If maintaining backward compatibility
with Verilog-1995 is a requirement, then always specify the exact size of
literal Z and X values.

The best way to avoid these Z and X fill gotchas is to take advantage of a
new System Verilog literal number, as described in Sec 4.6.


4.6 Filling vectors

Gotcha: Verilog does not have a literal value that fills all bits
of a vector with 1's.

In Verilog-2001, assigning 'bx, 'bz, or 0 will fill a vector of any size
with all bits set to X, Z or zero, respectively. However, assigning 'b1 is
not orthogonal. It does not fill a vector with all bits set to one.

//Verilog-2001 style:
parameter WIDTH = 64;
reg [WIDTH-1:0] data;

data = 'b0; // fills with 64'h0000000000000000
data = 'bz; // fills with 64'hzzzzzzzzzzzzzzzz
data = 'bx; // fills with 64'hxxxxxxxxxxxxxxxx
data = 'b1; // fills with 64'h0000000000000001 -- GOTCHA!

In order to assign a vector of any size with all bits set to one, designers
must learn clever coding tricks involving various Verilog operators. These
tricks are not discussed in this paper, because there is a better way to
avoid this gotcha...

How to avoid this gotcha: System Verilog defines a consistent syntax for
filling any size of variable with all 1s, all 0s, all Xs or all Zs.

//System Verilog style:
parameter WIDTH = 64;
reg [WIDTH-1:0] data;

data = '1; // fills with 64'hffffffffffffffff
data = '0; // fills with 64'h0000000000000000
data = 'z; // fills with 64'hzzzzzzzzzzzzzzzz
data = 'x; // fills with 64'hxxxxxxxxxxxxxxxx

The syntax for this is just a simple assigning '.


4.7 Passing real (floating point) numbers through ports

Gotcha: Verilog does not allow real numbers to be passed directly
through ports.

In Verilog, the outputs of a module can be either net or variable types, but
the signals receiving values from module instantiations are required to be
of type net. Verilog also requires that input ports of a module be net
types. Verilog variables include the real type, which is a double-precision
floating point value, but there is no counterpart to a real variable for the
net data types. If outputs of a module can be variable types, but the
receiving side must be a net type, how are real values passed through
module ports?

The gotcha is it's illegal in Verilog to pass real numbers through ports.
A secret that many engineers don't know, however, is that Verilog has a pair
of built-in system functions that can be used to convert real numbers to a
format that can be passed through ports. The numbers are then converted
back to real in the receiving module. These functions are $realtobits and
$bitstoreal.

module top;
wire [63:0] net_real; // only net types used in netlist
real_out ro (.net_real_out(net_real));
real_in ri (.net_real_in(net_real));
endmodule

module real_out(output wire [63:0] net_real_out); // output is net type
real r;
assign net_real_out = $realtobits(r); // must convert real to a
// bit-vector to pass through
// module output port
...
endmodule

module real_in(input wire [63:0] net_real_in); // input is net type
real r;
always @(net_real_in)
r = $bitstoreal(net_real_in); // must use bit-vector on input
// port, then convert to real
...
endmodule

How to avoid this gotcha: While Verilog does provide a solution for
passing real numbers through ports, the solution is not well known, and is
awkward to use. System Verilog provides a much more elegant way to avoid
this gotcha. In System Verilog, real types can be passed directly through
ports System Verilog also allows both the sending and receiving side of
ports to be real variables. The example above can be coded much more
simply in System Verilog.

module top;
real r; // variable types can be used in netlist
real_out ro (.r);
real_in ri (.r);
endmodule

module real_out(output real r); // output is real variable type
...
endmodule

module real_in(input real r); // input is real variable type
...
endmodule


4.8 Port connection rules

Gotcha: The size of a port and the size of the net or variable
connected to it can be different.

The Verilog standard states that module ports are treated as continuous
assign statements that continuously transfer values into, and out of,
modules. This is not a gotcha that one can avoid, but rather a rule that
helps explain some gotchas relating to port connections.

In Verilog, the receiving side of an input or inout port can only be a net
type. The transmitting side of an output port can be either a net or a
variable. When considering ports as continuous assignment statements, it
becomes easier to understand why the receiving sides of ports are required
to be net data type signals, and why the driver (or source) side of ports
could be either net or variable. The receiving side of a port is the same
as the left hand side of a continuous assign statement, and the driver or
source side of a port is the same as the right hand side of a continuous
assign statement. In other words, the left hand side/right hand side rules
for continuous assignments apply directly to port assignments.

With this in mind, consider the 4 scenarios regarding port size connections
(3 of which can be gotchas if not well understood):

- The port size and the signal driving the port are the same size
- The signal driving the port has more bits than the port (a gotcha)
- The signal driving the port has fewer bits than the port (a gotcha)
- An input port is unconnected; no signal driving the port (a gotcha)

Applying continuous assignment size rules to ports gives the following
effects for these 4 scenarios:

1. If the size of the port and the size of the signal driving the
port match, then the value passes through the port with no change.

2. If the signal driving the port has more bits than the port's
receiving signal, then the upper bits of the driving signal are
truncated, including any sign bit.

3. If the signal driving the port has fewer bits than the port's
receiving signal, then the upper bits are extended, following
Verilog's assignment rules:

- If the driving signal is unsigned, the upper bits are
zero-extended to the size of the receiving signal.
- If the driving signal is signed, then the upper bits will
be sign-extended.

4. If an input port is unconnected, the value for the receiving
signal of the port will be the default uninitialized value for its
given data type. For the wire net type, the uninitialized value
is Z. For tri0 and tri1 net types, the uninitialized values are
0 and 1, respectively, with a pull-up strength.

Most often, any mismatch in port connection sizes is a design error. But,
it is not a syntax error. In Verilog, an incorrect size declaration is very
easy design error to make, especially when the modules that make up a design
are written by several different engineers, (and possibly even come from
outside sources). A simple typo in a netlist, or an incorrect parameter
redefinition, can also lead to port size mismatches. Typographical errors
in a netlist can also result in ports of a module instance unintentionally
left unconnected.

Verilog's rules for port connection mismatches are well defined, but the
simulation results are a gotcha! Trying to trace back to why some bits
disappeared from a vector, or additional bits suddenly appeared, can be
difficult. And that assumes that verification detected that there is a
problem! The following example illustrates how values are extended or
truncated when passed through a port of a different size than the value.

module top;
wire [3:0] data = 4'b1111; // decimal 15
wire [7:0] address = 8'b11111111; // decimal 255

block1 b1 (.data(data), // 4-bit wire connected to 8-bit port
.address(address)); // 8-bit wire connected to 4-bit port
// third port left unconnected
endmodule: top

module block1 (input [7:0] data,
input [3:0] address,
input [3:0] byte_en);

initial
#1 $display(" data = %b \n address = %b \n byte_en = %b\n",
data, address, byte_en);
endmodule: block1

The output from this code is:

data = 00001111
address = 1111
byte_en = zzzz

The example above shows how confusing unconnected or partially connected
ports can be. The value of data has mysteriously changed, gaining an extra
four bits. The value of address changed from 255 to 15 (decimal), and
byte_en is high-impedance instead of a valid logic value.

Most simulators generate warnings when code like this is elaborated, but
such warnings are not required by the Verilog standard, and engineers are
notorious for ignoring these warnings.

System Verilog has a great solution to this: implicit port connections using
either . or .* module instantiations. When using the . or the
.* module instantiation syntax, the driver and receiver port signals are
required to be the same size. If, for some reason, a driver/receiver signal
pair size mismatch is desired, the port must be explicitly connected. This
makes it very obvious in the code that the mismatch was intended.

module top;
wire [7:0] data;
wire [7:0] address;

block1 b1 (.data, // implicit port connections
.address);
endmodule: top

module block1 (input [7:0] data,
input [3:0] address,
input [3:0] byte_en);
...
endmodule: block1

In this example, the size of the wire called data has been corrected to be
8-bits wide, which is the same as the size of the data port in block1. The
. shortcut will infer that the wire called data is connected to the
port called data. However, there is still a typo in the declaration of the
wire called address. Instead of a port connection mismatch (a gotcha), an
elaboration error will occur because the signal at the top level is a
different size than the block1 port. The . will not infer connections
that do not match in size.

The . method will allow unconnected ports, such as the byte_en port in
the example above. Was this port left unconnected on purpose, or is it
another typo in the netlist? To catch all the size mismatches & unconnected
ports, using the .* shortcut is the best solution.

module top;
wire [7:0] data;
wire [7:0] address;

block1 b1 (.*, // implicit port connection
.address(address[3:0]), // explicit connection mismatch
.byte_en() ); // explicit unconnected port
endmodule: top

module block1 (input [7:0] data,
input [3:0] address,
input [3:0] byte_en);
...
endmodule: block1

The .* shortcut requires explicitly listing all unconnected ports and all
the signals with different sizes.


4.9 Back-driven input ports

Gotcha: Verilog allows input ports to be used as outputs.

One of the surprising gotchas in Verilog is that a module input port can be
used as an output. If a designer mistakenly assigns a value to a signal
declared as an input port, there will not be any warnings or errors.
Instead, Verilog simply treats the input port as if it were a bidirectional
inout port. The Verilog Language Reference Manual refers to this a port
coercion. In this paper, we refer to an input port being used as an output
as a back-driven port.

The following example illustrates this surprising gotcha:

module top;
wire w1;
backdrive bd(.a(w1)); // instance of a module with back-driven port
endmodule

module backdrive(input wire a); // "a" will be coerced to be an
output
wire b;
assign a = b; // GOTCHA! the intent was to have b = a, not a = b;
endmodule

Even though signal a is an input to module backdrive, it can still be
assigned a value within backdrive. This has the effect of a having two
drivers wired together. This is legal because, in Verilog, ports are
treated as continuous assignments. The code above is equivalent to:

module top;
wire w1;
wire a, b;
assign a = w1; // same as connecting "w1" to input port "a"
assign a = b; // a second continuous assignment to "a"
endmodule

How to avoid this gotcha: With System Verilog, input ports can be connected
to variables, instead of the wire type. System Verilog restricts variables
to only allow a single source. This is different than a wire type, where
multiple drivers are permitted (whether intentional, or not). In the
preceding example, if "a" had been declared as a logic type instead of a
wire type, the assignment of a = b would be a syntax error, because it would
represent a second source for "a". The authors recommend that all module
inputs and outputs be declared as variable types, unless it is intended to
have multiple drivers on the port (e.g. a bidirectional data bus).

verilog shm dump

ncsim top_cfg -tcl -input dump.tcl

--- dump.tcl having -----
database -open -shm -default
probe -create -shm / -depth all -all
run
exit
----

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http://thinknow.tistory.com/225

http://www.gutenberg.org/wiki/Main_Page

http://voicesinthedark.com/content.php?iContent=50

http://www.loudlit.org/collection.htm

http://www.fullbooks.com/

http://www2.lib.virginia.edu/digitalcuration/etext.html

http://thinknow.tistory.com/216

http://ko.usmlelibrary.com/120

Manual Rooting, ADB, Gapps on the nook simple touch:

Setting up adb manually on the nook touch:

• If you want to restore, wipe data, or reset your nook, FIRST read how to backup your anotations and then search on this post for: Totally uninstall Gapps (my repack), unrooting, erasing and restoring.
• Download noogie, and burn it into an SD-card (http://www.multiupload.com/OFI609MP8V) use Win32DiskImage.exe.
• Shut down the Nook Touch completely your NST http://www.multiupload.com/CJ981FWPJG
• Insert the SD-card into your Nook, connect it to the pc and turn it on.
• When the nook ends booting (you should see a rooted forever splash screen on it) wait 20 seconds, you should see a new drive named boot, if not, go to MiniTool Partition Wizard Home Edition look for a partition named boot and assign it a letter.
• Open boot, and replace the uramdisk, with one of these (http://forum.xda-developers.com/show....php?t=1337653).
  This tuto is all made for the Wifi-uramdisk, if you want to use the usb change all the "adb connect yourNSTip" into "adb devices".
  
  If you finally want to use adb over usb, follow this to make the nook recognizable by adb http://forum.xda-developers.com/show...1&postcount=12or install this http://forum.xda-developers.com/show...3&postcount=11.
• Eject the nook from the pc and reboot the NST without the noogie SD-card.

Setting up root access on NST through adb and installing busybox:

• Download java JKD http://www.oracle.com/technetwork/ja...ads/index.html
• Download the android sdk (I recommend zipped) and extract it on C so that it looks like C:/android-sdk-windows
• Open the SDK manager and update it, install for example the 2.1 platform, etc, it will automatically create /platform-tools
• Download Superuser (http://nookdevs.com/images/a/a9/Superuser.zip), su (http://nookdevs.com/images/e/e0/Su.zip), and busybox (http://bit.ly/s1s7FZ or http://benno.id.au/android/busybox), extract them on C:/android-sdk-windows/platform-tools
• Connect your NST to your home Wi-Fi, and check its ip.
• Open cmd and type:
  
  
  

  
  

  http://forum.xda-developers.com/showthread.php?t=1380400

  
  

  
  

성격관련 영어표현

He is kind 그는 친절해요.
He is warm. 그는 따뜻해요.
He is generous. 그는 너그러워요.
He is optimistic. 그는 낙천적 이예요.
He is cheerful. 그는 명랑해요.
He is easy-going. 그는 느긋해요.
He is strong. 그는 강해요.
He is honest. 그는 정직해요.
He is sensitive. 그는 섬세해요.
He is extroverted. 그는 외향적 이예요.
He is ambitious. 그는 의욕적 이예요.
He is punctual. 그는 시간을 엄수해요.
He is reliable. 그는 믿음직해요.
He is flexible. 그는 유순해요.
He is hard-working. 그는 근면해요.
He is clever. 그는 영리해요.

What are her weaknesses? What are her faults?
그녀의 약점이 뭐예요?

She is unkind. 그녀는 불친절해요.
She is cold. 그녀는 냉정해요.
She is mean. 그녀는 비열해요.
She is pessimistic. 그녀는 비관적 이예요.
She is miserable. 그녀는 불쌍해요.
She is tense. 그녀는 긴장을 해요.
She is weak. 그녀는 약해요 .
She is dishonest. 그녀는 부정직해요.
She is insensitive. 그녀는 둔감해요.
She is introverted. 그녀는 내성적 이예요.
She is unambitious. 그녀는 의욕이 없어요.
She is always late. 그녀는 항상 늦어요.
She is unreliable. 그녀는 믿을 수 없어요.
She is inflexible. 그녀는 완고해요.
She is lazy. 그녀는 게을러요.
She is stupid. 그녀는 어리석어요.

저는 천성이 수줍어서 여가를 독서로 보내지요.
I am very shy by nature, and so I usually spend
my free time reading books.
저는 본래 침착하지 못해서 매일 실수를 하나씩 저지르지요.
I am very careless by nature and so I make at least
one blunder almost everyday.

- 사람의 성격을 positive(긍정적)와 negative(부정적)로
나누어보면....
* Positive - hardworking(근면한), creative(창의적인),
strict(엄격한), level-headed(분별있는) efficient(유능한),
punctual(꼼꼼한), reliable(믿음직한), generous(관대한),
* Negative - bad-tempered(심술궂은), impatient(성급한),
critical(비판적인), disorganized(혼란스러운), moody
(변덕스러운), forgetful(잘 잊는)

- Good Character (좋은 성격)

1. kind 친절한
2. honest 정직한
3. generous 관대한
4. merciful 자비로운
5. benevolent 자애로운
6. modest 겸손한
7. unselfish 이타적인
8. sincere 진실한
9. frank 솔직한
10. considerate 사려깊은
11. sympathetic 동정적인
12. humane 인정이 있는

-Bad character (나쁜 성격)

1. rude 무례한
2. impolite 무례한
3. dishonest 정직하지 않은
4. cruel 잔인한
5. ruthless 무자비한
6. greedy 탐욕스러운
7. mean 심술궂은
8. cunning 교활한
9. mischievous 짓궂은
10. malevolent 악의있는
11. selfish 이기적인
12. warlike 호전적인
13. negligent 태만한
14. jealous 질투심이 많은
15. brutal 잔혹한
16. hostile 적개심을 품은

- 인물의 성격~
active 활동적인, 적극적인
aggressive 공격적인, 침략적인
arrogant 거만한, 건방진
cold-blooded 냉정한
cold-blooded 냉혈한, 피도 눈물도 없는, 냉혹한
cold-hearted 냉담한, 무정한, unkind
communicative 이야기하기 좋아하는, 숨김없이 말하는
conservative 보수적인, 무사주의의
courageous 용기있는, 용감한
cruel 잔학한, 잔인한
extrovert 외향적인 사람
frank 솔직한
generous 관대한, 인심좋은, 대범한, 풍부한, 기름진
good-natured 본성이 착한
handicapped 심신장애의
hen-pecked 공처가의
hot-tempered 다혈질
ill-mannered 무뢰한
lofty 고상한, 지위높은, noble
notorious 악명높은
open-minded 포용력이 큰
people-oriented 사람지향적인, 사교적인
practical 실천적인, 실제로 쓸모있는
progressive 진보적인, 진보하는
reserved 체면 차린, 말없는, 수줍어하는
sociable 사교를 좋아하는
stern 엄격한, 완고한
stingy 인색한, 부족한
stubborn 완고한, 확고한
talented 재능이 있는
talkative 수다스러운
thoughtful 사려 깊은, 생각에 잠긴, 인정 많은
thoughtless 지각없는, 경솔한, 부주의한
timid 겁이 많은, 자신이 없는
unscientific 비과학적인, 비학술적인
whole-hearted 성의있는, 전심전력의
warm-blooded 열렬한, 격렬한, 정열적인

우리는 성격이 극과 극이에요.
We are totally different.

성격이 둥글둥글하다.
She is easygoing.

사람들은 외향적이라고 하는 데 사실은 내향적이예요.
Everyone thinks I"m an extrovert, but in fact I"m very shy
with strangers.

나는 우유부단한 성격이다.
I am really wishy-washy.
I am really bland.

기숙사 생활은 내 성격에 안 맞아요.
Dorm life is not for me.

자식은 양친의 성격을 이어 받는다.
Children have the qualities of the parents.

내 성격은 아부하고는 거리가 멀어.
Flattery is foreign to my nature.

전 성격이 좀 내성적이에요.
I"m a kind of introvert.

그녀는 성격이 아주 좋습니다.
She"s got a great personality

그가 성격이 좋다.
He has a "great personality". .

너무 느긋한 성격을 지니셨군요.
You have such a wishy-washy personality

그 쌍둥이는 성격이 매우 다르다
The twins have very different characters.

그는 꽤 무난한 성격이다.
He is rather a neutral character.

나도 적극적인지 소극적인지 모르겠다.
I"m not really sure whether I"m outgoing or reserved myself.

내 성격 많이 죽었다.
I"ve grown soft.
I"ve gone soft.
I"m not as tough as I used to be.
I"ve become a softy.

제 성격이 그래요
That"s my personality.

나는 음식에 대해서 좀 까다로운 편이다
I"m a picky eater.

나는 식성이 좋다.
I have a good appetite.

나는 뭐든지 먹을 수 있다.
I can it anything.

그는 허풍이 심해요.
He always talks big.
He has a big mouth.

그녀는 아주 영리하지만 게으르다고 할 수 있다.
She"s very clever, but she can be a lazy.

영리하다고는 할 수 없지만 근면한 편이다.
She"s not exactly witty, but she"s extremely hard-working.

쌍둥이라고 해도 성격은 하늘과 땅 차이예요.
There"s a world of difference in personalities between twins.
Twins have very different in personalities.
Twins have personalities that are like night and day.

그 사람은 성격이 아주 좋아요.
He has very good personality.

아주 마음이 따뜻해요.
He"s very warm guy.

좀 따분한 편이다.
Well, he"s rather boring.

좀 황당한 사람이다.
Oh, he"s a little overwhelming.

나는 붙임성 있다고 생각합니다.
I think I"m amiable.

우호적이고 사려가 깊다고 합니다.
People sometimes say I"m friendly and considerate.

감성적이고 관대하다고 생각합니다.
I think I"m both sensitive and big-hearted.

그 사람 성격이 어때요? (그는 어떤 사람입니까?)
What"s his personality?
What is he like?
What kind of person is he?
What kind of character is he?
What sort of person is he?
What type of person is he?

어떤 성격이세요?
What kind of personality do you think you have?

무슨 일에나 낙관적입니다.
I"m optimistic about everything.

좀 비관적인 성격입니다.
I"m sort of a pessimist.

건망증이 심하다.
I"m very forgetful.

말주변이 없습니다.
I"m afraid I"m a poor talker.

때때로 수다스럽습니다.
I sometimes speak too much.

그 사람은 성격이 급해요.
He is very impatient.
He is hot-tempered.

그는 사소한 일에 잔소리가 심한 사람이다.
He"s very particular about trivial things.

그녀는 마음이 좁고 완고한 것이 결점이다.
Her weakness is that she"s a bit narrow minded and obstinate.

그는 아마 그저 말이 없는 성격일 겁니다.
He"s probably just quiet.

당신은 참 개성적이요.
You have quite a personality.
You have a rich personality

나는 성질이 급해서 사소한 일에 때때로 쉽게 흥분합니다.
I"m rather short-tempered, and sometimes get easily excited
about unimportant things.

그 사람 성격이 시원시원해요.
He has a straightforward personality.

그는 활달하고 관대하고 머리가 좋은 사람이예요.
He"s lively, generous and clever.

나는 그리 강인한 성격이 못돼요.
I"m not that strong.

그렇게 사교적이지 못합니다.
I"m not really sociable.

심술궂은 편이다.
I"m rather mischievous.

전과 비교하면 숙기가 좋아졌습니다.
I"m now much outgoing than I used to be.

소극적인 편입니다.
I tend to be withdrawn.
I"m fairly reserved.

너 무지 뻔뻔한 애로구나.
You"re really arrogant.

그녀의 성격에 대해 비난하지 마라.
Do not cast aspersions on her character.

그의 열광적인 성격은 억제될 수 없었다.
언제나 그는 유쾌했다.
His ebullient nature could not be repressed
; he was always exuberant.

그의 성실성은 성격을 돋보이게 하였다.
His sincerity showed off his character.

성실한 여성입니다.
She is a sincere lady.

그들은 좀 괴팍하지만 좋은 사람들입니다.
The"re rather odd, but they"re good sorts.

I"m fed up with him.

I"m sick and tired of him.
그 사람이라면 진절머리가 나요.

She stood me up.
그녀가 나를 바람 맞췄어요.

I"ve had it up to here with this lousy job.
이 더러운 직장은 이제 더 이상 참을 수가 없습니다.

He was speaking off the top of his head.
그는 즉흥적으로 연설했죠.

Sometimes I think you"re very fickle.
이따금 당신은 꽤 변덕인 것 같아요.

It"s a pain in the neck.
정말 견디기 어려운 것이다.

Sometimes being frank is the best policy.

때로는 솔직하게 털어 놓는 것이 최선의 길이지요.

I didn"t mean to offend you.
기분을 상하게 하려고 한 말은 아니었습니다.

What are his merits? What are his strong points? 그의 장점이 뭐예요?

내용출처 : 하경호의 "Nothing ventured, nothing gained"