model for piecewise linear source

http://www.designers-guide.org/Forum/YaBB.pl?num=1270820173

Verilog-A pwl implementation using arrays for time/voltage input

`include "disciplines.vams"

module pwl(out);
output out;
electrical out;

parameter integer N = 1 from [2:inf);parameter real t[1:N] = {N{0}};
parameter real y[1:N] = {N{0}};

analog begin : blk
integer nxt_i;
real yp, tp, slope;
integer err;

        @(initial_step) begin
                nxt_i = 1;
                yp = y[1];
                tp = 0.0;
        end

        @(timer(t[nxt_i])) begin
                yp = y[nxt_i];
                tp = t[nxt_i];

                if(nxt_i < N) begin
                        nxt_i = nxt_i + 1;
                        if(t[nxt_i] - tp <= 0) begin
                                err = 1;
                                $debug("Non monotonic time sequence: t[%d] == %e, t[%d] == %e", nxt_i-1, tp, nxt_i, t[nxt_i]);
                                $finish;
                        end
                        if(!err)
                                slope = (y[nxt_i] - yp)/(t[nxt_i] - tp);
                end
        end

        if(!err)
                V(out) <+ yp + slope*($realtime - tp);

end

endmodule

System-Verilog pwl implementation

module strpwl(p, n);
   electrical p, n;
   inout p, n;

   parameter string pwl = "";
   parameter        dcval = 0.0;
  

   analog function real scanval;
      input s;
      inout pos;
      string s;
      integer pos;
      integer ipos;
      string  valstr;
            
      begin
         ipos = pos;
         while(pos < s.len() && s.substr(pos, pos) != ",")
           pos = pos+1;

         valstr = s.substr(ipos, pos-1);
         if(1 == $sscanf(valstr, "%g", scanval))
           pos = pos+1;
         else
           pos = -1;  // Error indicator
      end
   endfunction

   integer pos = 0;
   real    tnext, vnext;
   real    tprev = 0.0;
   real    vprev = dcval;
   real    slope;
  
   integer err;
  
   analog initial begin : blk
      real retVal;

      tprev = 0.0;
      vprev = dcval;
      
      tnext = scanval(pwl, pos);
      vnext = scanval(pwl, pos);
      if (tnext-tprev != 0.0)
          slope = (vnext - vprev)/(tnext - tprev);
      $strobe(tnext, vnext);
   end

   analog begin
      @(timer(tnext)) begin
         tprev = tnext;
         vprev = vnext;
        
         tnext = scanval(pwl, pos);
         vnext = scanval(pwl, pos);

         if(pos > 0)
           begin
              if(tnext - tprev <= 0) begin
                 err = 1;
                 $debug("Non monotonic time sequence.");
                 $finish;
              end
              if(!err)
                slope = (vnext - vprev)/(tnext - tprev);
           end
      end

      if(!err)
        V(p, n) <+ vprev + slope*($abstime - tprev);

   end

endmodule
 

Furnace

https://www.alsplumbing.com/gas-furnace-failure-why/

Standard Efficiency (80%) Gas Furnace

High-Efficiency Gas Furnace (95%)

lecture link

Sam Palermo
ECEN 689: Optical Interconnects Circuits and Systems
ECEN 720: High-Speed Links Circuits and Systems
High-Speed Links Circuit Design Techniques Short Course


A 10Gb/s Compact Low-Power Serial I/O with DFE-IIR Equalization in 65nm CMOS
hslink_eq_overview_hanumolu_jhses05.pdf

Controlled Intersymbol Interference Design Techniques of Conventional Interconnect Systems for Data Rates Beyond 20 Gbps


Modeling, Simulation, and Design of a Multi-Mode 2-10 Gb/sec Fully Adaptive Serial Link System

Pattern Generator Model for Jitter-Tolerance Simulation
Modeling Jitter in PLL-based Frequency Synthesizers

Modeling and Verification of High-Speed Wired Links with Verilog-AMS

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 9, SEPTEMBER 2008
Edge and Data Adaptive Equalization of Serial-Link Transceivers
Koon-Lun Jackie Wong, E-Hung Chen, and Chih-Kong Ken Yang, Senior Member, IEEE

Clock and Data Recovery Circuit and Clock Synthesizers for 40 Gb/s High-Density Serial I/O-Links in 90-nm CMOS
ABHANDLUNG
zur Erlangung des Titels


verilog piecewise linear behavioral modeling for mixed-signal

INTRODUCTION TO DIGITAL FILTERS

Art of approximation in science and engineering

Accurate and Efficient Modeling Approach for PhaseLocked Loops for Mixed-Signal

Phase Noise Simulation and Modeling of ADPLL by SystemVerilog

All digital phase-locked loop: concepts, design and applications

Metastability

Real Portable Models for System/Verilog/A/AMS 

spec link

Serial ATA Revision 3.0
 http://www.lttconn.com/res/lttconn/pdres/201005/20100521170123066.pdf

Clock and Data Recovery/Buffer Memory (Elastic Buffer)

https://en.wikibooks.org/wiki/Clock_and_Data_Recovery/Buffer_Memory_(Elastic_Buffer)

Clock and Data Recovery/Buffer Memory (Elastic Buffer)/Cascades of Buffers and CDRs, delays and tolerance

https://en.wikibooks.org/wiki/Clock_and_Data_Recovery/Buffer_Memory_(Elastic_Buffer)/Cascades_of_Buffers_and_CDRs,_delays_and_tolerance

1G/2.5G Ethernet PCS/PMA or SGMII v15.0

https://www.xilinx.com/support/documentation/ip_documentation/gig_ethernet_pcs_pma/v15_0/pg047-gig-eth-pcs-pma.pdf

1G/2.5G Ethernet PCS/PMA or SGMII v16.0

https://www.xilinx.com/support/documentation/ip_documentation/gig_ethernet_pcs_pma/v16_0/pg047-gig-eth-pcs-pma.pdf

10G Ethernet PCS/PMA v6.0

https://www.xilinx.com/support/documentation/ip_documentation/ten_gig_eth_pcs_pma/v6_0/pg068-ten-gig-eth-pcs-pma.pdf

IEEE 802.3by 25G Ethernet TF A BASELINE PROPOSAL FOR RS, PCS, AND FEC

http://www.ieee802.org/3/by/public/Jan15/baden_3by_01b_0115.pdf

IPG Considerations

http://www.ieee802.org/3/ba/public/may08/folkens_01_0508.pdf

Physical Coding Sublayer

https://en.wikipedia.org/wiki/Physical_Coding_Sublayer

vim tip

Changing case with regular expressions

For example, assume a line with the text "This is a test".

:s/\(test\)/\U\1 file/

produces: This is a TEST FILE

:s/\(test\)/\U\1\e file/

produces: This is a TEST file

http://vim.wikia.com/wiki/Changing_case_with_regular_expressions

Change filenames and replace string within files

Change filenames and replace string within files.

import os
import fnmatch
import shutil
import re

for file in os.listdir('.'):
    if fnmatch.fnmatch(file, 'pattern_*.v'):
        p = re.compile('pattern_')
        dest = 'new_dir/' + p.sub('new_pattern_',file)
        print 'new_dir/' + dest
        shutil.copyfile(file, dest)

        with open(dest, 'r') as file:
            filedata = file.read()
        filedata = filedata.replace('pattern_', 'new_pattern_')

        flag = True
        newfile = ""
        for line in filedata.splitlines():
            if re.search(r"^.ifdef", line):
                flag = True
                continue
            elif re.search(r"^.else", line):
                flag = False
            elif re.search(r"^.endif", line):
                flag = True
                continue
            if flag :
                newfile = newfile + line + '\n'

        with open(dest, 'w') as file:
            file.write(newfile)
            #file.write(filedata)

SystemVerilog DPI in irun

module real_test ();

// map the C function name to the Verilog function name

import "DPI-C" context get_real_c = function real get_real_v ();

import "DPI-C" context put_real_c = function void put_real_v (real x);     

real pi;

initial

begin

$display("real_test");

pi = get_real_v();        // get a real number from the C code

$display("pi = %f", pi);  // display it

put_real_v(pi);           // send the real number back to C code  

  

end

endmodule

#include "svdpi.h"

// since we are using math functions, include the math library

#include <math.h>

// can use io_printf() instead of printf() to put into ncsim.log file

double get_real_c() {  // imported SV function

  // exercise DPI function - get calling scope

  printf("Function Calling HDL scope is %s \n", svGetNameFromScope(svGetScope() ) );

  return 3.14159;

}

void put_real_c(double n) {  // imported SV function

  // exercise DPI function - get calling scope

  printf("Function Calling HDL scope is %s \n", svGetNameFromScope(svGetScope() ) );

  printf("pi + 5.0 = %f\n", n+5.0);      

}

gcc -fPIC -g -shared -o libdpi.so  real_dpi.c  -I/`ncroot`/tools/include

irun -64 real_test.sv

or

ncvlog real_test.v -sv

ncelab -dpiheader dpi.h worklib.real_test:module

ncsim worklib.real_test:module -sv_lib libdpi.so  -sv_root .