- If the left-most bit of value is 0 or 1, the value is left-extended with 0
- If the left-most bit of value is Z, the value is left-extended with Z
- If the left-most bit of value is X, the value is left-extended with X
- But…a signed value is not sign-extended!
8’hA unsigned value extends to 00001010
8’shA signed value extends to 00001010
There are two types of operators in Verilog and SystemVerilog
- Self-determined operators do not modify their operand(s)
- Context-determined operators modify all operands to have the same size, using zero-extension or sign-extension
http://www.uccs.edu/~gtumbush/published_papers/Tumbush%20DVCon%2005.pdf
module add_signed_1995 (
input [2:0] A,
input [2:0] B,
output [3:0] Sum );
assign Sum = {A[2],A} + {B[2],B};
endmodule // add_signed_1995
Code Example 1: Addition - Verilog 1995
module add_signed_2001 (
input signed [2:0] A,
input signed [2:0] B,
output signed [3:0] Sum );
assign Sum = A + B;
endmodule // add_signed_2001
Code Example 2: Addition - Verilog 2001
input [2:0] A,
input [2:0] B,
input carry_in,
output [3:0] Sum );
assign Sum = {A[2],A} + {B[2],B} + carry_in;
endmodule // add_carry_signed_1995
Code Example 3: Add with Carry - Verilog 1995
module add_carry_signed_2001 (
input signed [2:0] A,
input signed [2:0] B,
input carry_in,
output signed [3:0] Sum );
assign Sum = A + B + carry_in;
endmodule // add_carry_signed_2001
Code Example 4: Addition with Carry – Incorrect
module add_carry_signed_final (
input signed [2:0] A,
input signed [2:0] B,
input carry_in,
output signed [3:0] Sum );
assign Sum = A + B + $signed({1'b0,carry_in}); ;
endmodule // add_carry_signed_final
Code Example 5: Add with Carry - Correct
http://web.mit.edu/6.111/www/f2012/handouts/L08.pdf
