lecture link

Sam Palermo
ECEN 689: Optical Interconnects Circuits and Systems
ECEN 720: High-Speed Links Circuits and Systems
High-Speed Links Circuit Design Techniques Short Course


A 10Gb/s Compact Low-Power Serial I/O with DFE-IIR Equalization in 65nm CMOS
hslink_eq_overview_hanumolu_jhses05.pdf

Controlled Intersymbol Interference Design Techniques of Conventional Interconnect Systems for Data Rates Beyond 20 Gbps


Modeling, Simulation, and Design of a Multi-Mode 2-10 Gb/sec Fully Adaptive Serial Link System

Pattern Generator Model for Jitter-Tolerance Simulation
Modeling Jitter in PLL-based Frequency Synthesizers

Modeling and Verification of High-Speed Wired Links with Verilog-AMS

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 9, SEPTEMBER 2008
Edge and Data Adaptive Equalization of Serial-Link Transceivers
Koon-Lun Jackie Wong, E-Hung Chen, and Chih-Kong Ken Yang, Senior Member, IEEE

Clock and Data Recovery Circuit and Clock Synthesizers for 40 Gb/s High-Density Serial I/O-Links in 90-nm CMOS
ABHANDLUNG
zur Erlangung des Titels


verilog piecewise linear behavioral modeling for mixed-signal

INTRODUCTION TO DIGITAL FILTERS

Art of approximation in science and engineering

Accurate and Efficient Modeling Approach for PhaseLocked Loops for Mixed-Signal

Phase Noise Simulation and Modeling of ADPLL by SystemVerilog

All digital phase-locked loop: concepts, design and applications

Metastability

Real Portable Models for System/Verilog/A/AMS