Recent versions allow you to insert AUTOS in non-AUTO designs, so IP interconnect can be easily modified. You can also expand SystemVerilog ".*" port instantiations, to see what ports will be connected by the simulators.
emacs –f verilog-batch-auto {filename.v}
emacs -batch {filename.v} -f verilog-auto -f save-buffer
emacs -batch {filename.v} -f verilog-auto -f save-buffer
/*AUTOARG*/ parses the input/output/inout statements.
/*AUTOWIRE*/ takes the outputs of sub modules and declares wires for them (if needed -- you can declare them yourself).
/*AUTOREG*/ saves having to duplicate reg statements for nets declared as outputs. (If it’s declared as a wire, it will be ignored, of course.)
AUTOINOUTMODULE will copy I/O from another module. AUTOTIEOFF will terminate undriven outputs, and AUTOUNUSED will terminate unused inputs.
/*AUTOINST*/ Look for the submod.v file, read its in/outputs.
Keep signal names consistent!
Note the simplest and most obvious case is to have the signal name on the upper level of hierarchy match the name on the lower level. Try to do this when possible.
Occasionally two designers will interconnect designs with different names. Rather then just connecting
them up, it’s a 30 second job to use vrename from Verilog-Perl suite to make them consistent.
Method 1: AUTO_TEMPLATE lists
exceptions for “submod.” The ports need not exist. (This is better if submod occurs many times.)
@ in the template takes the leading digits from the reference.(Or next slide.)
[] takes the bit range for the bus from the referenced module. Generally, always just add [].
Instantiations using RegExps
Method 2: List the signal before the AUTOINST. First put a // Input or // Output comment for AUTOWIRE.
See Cliff Cumming’s Paper
http://www.sunburst-design.com/papers/CummingsSNUG2007Boston_DotStarPorts.pdf
Where to Find Modules
// Local Variables:
// verilog-auto-library-flags:(”–f ../../input.vc”)
// End:
// input.vc
-y dir1
-y dir2
Techniques to exclude signals from AUTOOUTPUT (or AUTOINPUT etc).
1. Declare “fake” output
2. Use inclusive regexp
3. Set the output ignore regexp
#!/bin/bash
/*AUTOREG*/ saves having to duplicate reg statements for nets declared as outputs. (If it’s declared as a wire, it will be ignored, of course.)
AUTOINOUTMODULE will copy I/O from another module. AUTOTIEOFF will terminate undriven outputs, and AUTOUNUSED will terminate unused inputs.
/*AUTOINST*/ Look for the submod.v file, read its in/outputs.
Keep signal names consistent!
Note the simplest and most obvious case is to have the signal name on the upper level of hierarchy match the name on the lower level. Try to do this when possible.
Occasionally two designers will interconnect designs with different names. Rather then just connecting
them up, it’s a 30 second job to use vrename from Verilog-Perl suite to make them consistent.
Method 1: AUTO_TEMPLATE lists
exceptions for “submod.” The ports need not exist. (This is better if submod occurs many times.)
@ in the template takes the leading digits from the reference.(Or next slide.)
[] takes the bit range for the bus from the referenced module. Generally, always just add [].
Instantiations using RegExps
Method 2: List the signal before the AUTOINST. First put a // Input or // Output comment for AUTOWIRE.
See Cliff Cumming’s Paper
http://www.sunburst-design.com/papers/CummingsSNUG2007Boston_DotStarPorts.pdf
Where to Find Modules
// Local Variables:
// verilog-auto-library-flags:(”–f ../../input.vc”)
// End:
// input.vc
-y dir1
-y dir2
You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. For example the same expansion will result from only extracting outputs starting with ov:
Techniques to exclude signals from AUTOOUTPUT (or AUTOINPUT etc).
1. Declare “fake” output
2. Use inclusive regexp
3. Set the output ignore regexp
#!/bin/bash
for i in "$@"
do
xemacs -batch $i -f verilog-batch-auto -f save-buffer
done