http://www.lttconn.com/res/lttconn/pdres/201005/20100521170123066.pdf
Clock and Data Recovery/Buffer Memory (Elastic Buffer)
https://en.wikibooks.org/wiki/Clock_and_Data_Recovery/Buffer_Memory_(Elastic_Buffer)
Clock and Data Recovery/Buffer Memory (Elastic Buffer)/Cascades of Buffers and CDRs, delays and tolerance
https://en.wikibooks.org/wiki/Clock_and_Data_Recovery/Buffer_Memory_(Elastic_Buffer)/Cascades_of_Buffers_and_CDRs,_delays_and_tolerance
1G/2.5G Ethernet
PCS/PMA or SGMII v15.0
https://www.xilinx.com/support/documentation/ip_documentation/gig_ethernet_pcs_pma/v15_0/pg047-gig-eth-pcs-pma.pdf
1G/2.5G Ethernet
PCS/PMA or SGMII v16.0
https://www.xilinx.com/support/documentation/ip_documentation/gig_ethernet_pcs_pma/v16_0/pg047-gig-eth-pcs-pma.pdf
10G Ethernet PCS/PMA
v6.0
https://www.xilinx.com/support/documentation/ip_documentation/ten_gig_eth_pcs_pma/v6_0/pg068-ten-gig-eth-pcs-pma.pdf
IEEE 802.3by 25G Ethernet TF
A BASELINE PROPOSAL FOR RS, PCS, AND FEC
http://www.ieee802.org/3/by/public/Jan15/baden_3by_01b_0115.pdf
IPG Considerations
http://www.ieee802.org/3/ba/public/may08/folkens_01_0508.pdf
Physical Coding Sublayer
https://en.wikipedia.org/wiki/Physical_Coding_Sublayer