The IEEE Verilog 1364-2001 Standard What's New, and Why You Need It

http://www.sutherland-hdl.com/papers/2000-HDLCon-paper_Verilog-2000.pdf


3.2 Scalable models—Verilog generate


Verilog-2001 adds  generate loops, which permit generating multiple instances of modules and primitives, as well as generating multiple occurrences of variables, nets, tasks, functions, continuous assignments, initial procedures, and always procedures. Generated declarations and instantiations can be conditionally created, using if–else decisions and case statements.

3.4 Indexed vector part selects

The Verilog-2001 standard adds a new syntax, called indexed part selects. With an indexed part select, a base expression, a width expression, and an offset direction are provided, in the form of:
[base_expr +: width_expr] //positive offset
[base_expr -: width_expr] //negative offset




3.5 Multidimensional arrays
The Verilog-1995 standard allows one-dimensional arrays of variables. Verilog-2001 extends this by permitting:
• Multi-dimensional arrays
• Arrays of both variable and net data types