http://www.veripool.org/papers/verilog-mode_veritedium_snug.pdf
Reduce spins on fixing lint or compiler warnings
Reduce sensitivity problems
- If you forget (or don’t have) a linter, these are horrible to debug!
Make it easier to name signals consistently
through the hierarchy
- Reduce cut & paste errors on multiple instantiations.
- Make it more obvious what a signal does.
Reducing the number of lines is goodness alone.
- Less code to "look" at.
- Less time typing.
This expansion is best if in the editor
• You can “see” the expansion and edit as needed
There is a Verilog package for Emacs
• Written by Michael McNamara <mac@versity.com>
• Auto highlighting of keywords
• Standardized indentation
Expanded it to read & expand /*AUTOs*/
• Magic key sequence for expand/deexpand
C-c C-a and C-c C-d
With this key sequence,
Verilog-Mode parses the verilog code, and
expands the text after any /*AUTO*/ comments.
Friday, April 13, 2012
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